Method for preventing gate depletion effects of MOS transistor

ABSTRACT

The present invention shows a method of fabricating a MOS transistor on the substrate of a semiconductor wafer and of preventing the gate depletion effects occurring in the MOS transistor. The method involves first forming a silicon oxide layer on the substrate. Then an amorphous silicon layer is formed on the silicon oxide layer followed by forming a silicon germanium (Si 1-x Ge x , x=0.05˜1.0) layer on the amorphous silicon layer. Thereafter, an etching process removes portions of the silicon germanium layer and the amorphous silicon layer so as to form gates of the MOS transistor on the substrate. Finally, a spacer is formed around each gate and a source and a drain of each MOS transistor is formed in the substrate.

BACKGROUND OF THE INVENTION

[0001] 1. Field of the Invention

[0002] The present invention relates to a method of forming ametal-oxide semiconductor (MOS) transistor, and more particularly, to amethod of preventing gate depletion effects occurring in the MOStransistor.

[0003] 2. Description of the Prior Art

[0004] With the development of very large scale integration (VLSI), thelow electricity consumption and high integration ofmetal-oxide-semiconductor (MOS) transistors allows them to be widelyapplied in the semiconductor process. Usually, a MOS transistorcomprises a gate and two semiconductor regions, called a source anddrain located on each side of a capacitor with an electricalcharacteristic opposite to that of the silicon substrate. The majorstructure of the gate is composed of a gate oxide layer and a gateconductive layer. When a proper bias is added to the gate, the MOStransistor can be regarded as a solid switch to control the connectionof current.

[0005] Please refer to FIG. 1 to FIG. 4. FIG. 1 to FIG. 4 are schematicdiagrams of fabricating a MOS transistor according to the prior art. Asshown in FIG. 1, a semiconductor wafer 10 comprises a silicon substrate12 and plurality of both field oxides 14 and channel stops 16. In theprior art, the fabricating technique of the MOS transistor firstinvolves placing the semiconductor wafer 10 in a furnace, followed byinjecting oxygen into at atmospheric pressure. Thus, by using dryoxidation, the single crystal silicon on the surface of the active areais oxidized to become a silicon oxide layer 18 with a thickness of100-250 angstroms. The silicon oxide layer 18 is used as a gate oxide.

[0006] A low-pressure CVD (LPCVD) process is then performed to depositan undoped polysilicon layer 20, with a thickness of 1000-2000angstroms, on the surface of semiconductor wafer 10 to function as agate conductive layer. After the formation of the undoped polysiliconlayer 20, a patterned photoresist layer 22 is formed on the surface ofthe undoped polysilicon layer 20 to define the pattern and the positionof a gate. As shown in FIG. 2, the pattern of the photoresist layer 22is used as a hardmask to perform an anisotropic etching process toremove both the undoped polysilicon layer 20 and the silicon oxide layer18 uncovered by the hardmask down to the surface of the siliconsubstrate 12. Then, the photoresist layer 22 is removed to complete theformation of a gate 24.

[0007] As shown in FIG. 3, a silicon nitride (Si₃N₄) 26 is deposited onthe surface of the semiconductor wafer 10. As shown in FIG. 4, ananisotropic etching process is then used to form a spacer 28 on eitherside of the gate 24. Finally, an ion implantation process is performed,using the spacer 28 as a mask, to form a source 32 and drain 34 of theMOS transistor and complete the fabrication of the MOS transistor. Thedistance L between the source 32 and drain 34 is the channel length. Theundoped polysilicon layer 20 comprising the gate 24 is implanted as adoped polysilicon layer during the ion implantation process performedfor forming a source and a drain of each PMOS and NMOS transistor.

[0008] After performing the ion implantation process, an annealingprocess is performed to uniformly diffuse dopants in the undopedpolysilicon layer 20 and to simultaneously drive dopants into the source32 and drain 34. Gate depletion effects occur when the annealing processinsufficiently drives the dopants down the entire depth of the gate 24.As shown in FIG. 5, a portion of the gate nearest the gate oxide layer18 is depleted of dopants and behaves as an insulating region 30. As aresult, the MOS transistor behaves as though the gate oxide layer 18 issubstantially thicker, thereby resulting in signal delay of the gate anda substantial degradation in device performance.

[0009] Various techniques have been proposed to reduce gate depletioneffects, the simplest method is to increase implantation dosage.However, because of the poly grain boundaries and the different dopantsegregation at the poly/SiO2 interface, increasing the implant dose notnecessarily increase the dopant concentration proportionally. Also,unless the gate oxide layer has good resistance to boron penetration,increasing the boron dose usually results in a boron penetration effectof a PMOS transistor.

SUMMARY OF THE INVENTION

[0010] It is therefore a primary objective of the present invention toprovide a method for preventing gate depletion effects occurring in theMOS transistor to solve the above-mentioned problem.

[0011] In the preferred embodiment, the method is first forming asilicon oxide layer on the substrate of a semiconductor wafer. Then anamorphous silicon layer is formed on the silicon oxide layer followed byforming a silicon germanium (Si_(1-x)Ge_(x), x=0.05˜1.0) layer on theamorphous silicon layer. Thereafter, an etching process is performed toremove portions of the silicon germanium layer and the amorphous siliconlayer to form a gate of the MOS transistor on the substrate. Finally, aspacer is formed around each gate and a source and a drain of each MOStransistor is formed in the substrate.

[0012] The present invention method uses a silicon germanium layer andan amorphous silicon layer as a gate conductive layer of the MOStransistor so as to increase active dopant concentration in theconductive layer and inhibit gate depletion effects.

[0013] These and other objectives of the present invention will no doubtbecome obvious to those of ordinary skill in the art after reading thefollowing detailed description of the preferred embodiment, which isillustrated in the various figures and drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

[0014]FIG. 1 to FIG. 4 are schematic diagrams of a method of fabricatinga MOS transistor according to the prior art.

[0015]FIG. 5 is a schematic diagram of gate depletion effects occurringin the MOS transistor.

[0016]FIG. 6 to FIG. 8 are schematic diagrams of a method of fabricatinga MOS transistor according to the present invention.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0017] Please refer to FIG. 6 to FIG. 8 of schematic diagrams offabricating a PMOS or an NMOS transistor according to the presentinvention. Additionally, the present invention is also applied tofabricate a nitride read only memory (NROM) device in a peripheralregion. As shown in FIG. 6, a semiconductor wafer 40 comprises a siliconsubstrate 42 and plurality of both field oxides 44 and channel stops 46.The field oxide 44 functions only in isolating and defining the positionof an active area 41. However, other isolation methods are alsoapplicable to the present invention, whereby a shallow trench isolation(STI) structure can be used to replace the field oxide 44 of FIG. 6.

[0018] As shown in FIG. 6, the method of present invention firstinvolves oxidizing the surface of silicon substrate 42 in the activearea 41 to form a silicon oxide layer 48 with a thickness of 100-250angstroms. The silicon oxide layer 48 is used as a gate oxide of the MOStransistor. Then an amorphous silicon layer 50 with a thickness of700-1000 angstroms (A) and a poly silicon germanium (Si_(1-x)Ge_(x),x=0.05˜1.0) layer 52 with a thickness of 1100˜1500 angstroms (Å) arerespectively formed on the surface of semiconductor wafer 40. Both theamorphous silicon layer 50 and poly silicon germanium layer 52 are usedas a gate conductive layer. The silicon germanium layer 52 is formed byperforming a chemical vapor deposition (CVD) process aerating silane(SiH₄), germane (GeH₄) and hydrogen at a temperature between 450° C. and620° C.

[0019] As shown in FIG. 7, a patterned photoresist layer (not shown) isformed on the silicon germanium layer 52 to define patterns of gate. Thepatterned photoresist layer is used as a hard mask to perform ananisotropic etching process for removing the silicon germanium layer 52,the amorphous silicon layer 50 and the silicon oxide layer 48 notcovered by the hard mask until the surface of the silicon substrate 42.Thereafter, the photoresist layer is removed to complete the process offabricating a gate 54 structure.

[0020] Finally, as shown in FIG. 8, a first ion implantation process isfirst performed to form a lightly doped drain (LDD) 55 of the MOStransistor. Then a silicon nitride compound is deposited on the surfaceof the semiconductor wafer 40 followed by performing an anisotropicetching process to form a spacer 56 around the gate 54. Thereafter, thespacer 56 is used as a mask to perform a second ion plantation processso as to form two doped areas on two sides of the gate 54 on the siliconsubstrate 42. Then a high temperature annealing process is performed todrive the dopants into the two doped areas for forming a source 58 and adrain 60 of the MOS transistor. Thus far, the fabrication of MOStransistor is completed according to the present invention.

[0021] The MOS transistor according to the present invention uses asilicon germanium layer stack on an amorphous silicon layer as the gateconductive layer. As well, the high temperature annealing processperformed after the formation of the source and drain diffuses germaniumatoms in the silicon germanium layer into the amorphous silicon layer soas to transform the amorphous silicon layer to silicon germanium,furthermore, to suppress gate depletion effects occurring in the MOStransistor.

[0022] In contrast to the MOS transistor fabricated by the prior art,the MOS transistor according to the present invention uses a silicongermanium layer and an amorphous silicon layer as a gate conductivelayer so as to increase active dopant concentration in the conductivelayer and reduce signal delay caused by gate depletion effects. As well,the amorphous silicon layer will improve the quality of the gate oxidelayer and increase the integrity of the oxide layer.

[0023] Those skilled in the art will readily observe that numerousmodifications and alterations of the device may be made while retainingthe teachings of the invention. Accordingly, the above disclosure shouldbe construed as limited only by the metes and bounds of the appendedclaims.

What is claimed is:
 1. A method of forming a metal-oxide semiconductor(MOS) transistor on a substrate of a semiconductor wafer and ofpreventing gate depletion effects occurring in the MOS transistor, themethod comprising: forming a silicon oxide layer on the substrate;forming an amorphous silicon layer on the silicon oxide layer; forming asilicon germanium layer on the amorphous silicon layer; performing anetching process to etch the silicon germanium layer and the amorphoussilicon layer so as to form a gate of the MOS transistor on thesubstrate; forming a spacer around the gate; and forming a source and adrain of the MOS transistor in the substrate.
 2. The method of claim 1wherein the substrate is a silicon substrate.
 3. The method of claim 1wherein the chemical composition of the silicon germanium layer isSi_(1-x)Ge_(x), x=0.05˜1.0.
 4. The method of claim 1 wherein the siliconoxide layer is used as a gate oxide of the MOS transistor.
 5. The methodof claim 1 wherein the etching process also etches the silicon oxidelayer.
 6. The method of claim 1 wherein the amorphous silicon layer andthe polysilicon layer are used as a gate electrode of the MOStransistor.
 7. The method of claim 1 wherein the MOS transistor is ann-type MOS transistor (NMOS), or a p-type MOS transistor (PMOS).
 8. Themethod of claim 1 wherein a first ion implantation process is comprisedto form a lightly doped drain (LDD) of the MOS transistor.
 9. The methodof claim 1 wherein the method of forming the source and drain comprise:performing a second ion implantation process to form two doped areas ontwo sides of the gate on the substrate; and performing a hightemperature annealing process to drive the dopants into the two dopedareas for forming the source and drain.
 10. The method of claim 9wherein the high temperature annealing process diffuses germanium atomsin the silicon germanium layer into the amorphous silicon layer so as totransform the amorphous silicon layer to silicon germanium, furthermore,to suppress gate depletion effects occurring in the MOS transistor. 11.The method of claim 1 wherein the silicon germanium layer is formed byperforming a chemical vapor deposition (CVD) process aerating silane(SiH₄), germane (GeH₄) and hydrogen at a temperature between 450° C. and620° C.
 12. A MOS transistor fabricating method of preventing gatedepletion effects occurring in the MOS transistor, the methodcomprising: providing a semiconductor wafer; forming a silicon oxidelayer on the silicon substrate of the semiconductor wafer; forming anamorphous silicon layer on the silicon oxide layer; performing anin-situ doped chemical vapor deposition (CVD) process for forming asilicon germanium layer on the amorphous silicon layer; performing anetching process to etch the silicon germanium layer and the amorphoussilicon layer so as to form a gate of the transistor on the substrate;forming a spacer around the gate; performing a first ion implantationprocess to form two doped areas on two sides of the gate on the siliconsubstrate; and performing a high temperature annealing process to drivein the dopants in the two doped areas for forming a source and a drainof the MOS transistor; wherein the high temperature annealing processdiffuses germanium atoms in the silicon germanium layer into theamorphous silicon layer so as to transform the amorphous silicon layerto silicon germanium, furthermore, to suppress gate depletion effectsoccurring in the MOS transistor.
 13. The method of claim 12 wherein thesilicon oxide layer is used as a gate oxide of the MOS transistor. 14.The method of claim 12 wherein the chemical composition of the silicongermanium layer is Si_(1-x)Ge_(x), x=0.05˜1.0.
 15. The method of claim12 wherein the etching process also etches the silicon oxide layer. 16.The method of claim 12 wherein the amorphous silicon layer and thepolysilicon layer are used as a gate electrode of the MOS transistor.17. The method of claim 12 wherein the MOS transistor is an n-type MOStransistor (NMOS), or a p-type MOS transistor (PMOS).
 18. The method ofclaim 12 wherein a second ion implantation process is also comprised toform a lightly doped drain (LDD) of the MOS transistor.
 19. The methodof claim 12 wherein the reaction gases of the in-situ doped chemicalvapor deposition (CVD) process comprise silane (SiH₄), germane (GeH₄)and hydrogen, and the deposition temperature of the in-situ doped CVDprocess is between 450° C. and 620° C.